Mentor Graphics' Verification Academy

Mentor Graphics' Verification Academy is a first of its kind—unlike anything in the industry. Its goals are to provide the skills necessary to mature an organization's advanced functional verification process capabilities. To this end, the Verification Academy provides a methodological bridge between high-level value propositions (related to advanced verification technology) and the low-level details (related to specific tool and verification language details).

https://verificationacademy.com/

SPICE LEVEL 3 MOSFET MODEL

*TAKEN  VDD=5V,LMIN=1U
.MODEL MbreakN-X NMOS (LEVEL = 3
+ TOX = 200E-10 NSUB = 1e17 GAMMA = 0.5
+ PHI = 0.7 VTO = 0.8 DELTA = 3.0
+ UO = 650 ETA = 3.0E-6 THETA = 0.1
+ KP = 120E-6 VMAX = 1E5 KAPPA = 0.3
+ RSH = 0 NFS = 1E12 TPG = 1
+ XJ = 500E-9 LD = 100E-9
+ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10
+ CJ = 400E-6 PB = 1 MJ = 0.5
+ CJSW = 300E-12 MJSW = 0.5
+  LAMBDA=0.01 )
*$




.MODEL MbreakP-X PMOS (LEVEL = 3
+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6
+ PHI = 0.7 VTO = -0.9 DELTA = 0.1
+ UO = 250 ETA = 0 THETA = 0.1
+ KP = 40E-6 VMAX = 5E4 KAPPA = 1
+ RSH = 0 NFS = 1E12 TPG = -1
+ XJ = 500E-9 LD = 100E-9
+ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10
+ CJ = 400E-6 PB = 1 MJ = 0.5
+ CJSW = 300E-12 MJSW = 0.5
+ LAMBDA=0.0125 )
*$

BSIM MODEL VERSON 3.2 ORCAD16.0 PSPICE

******LMIN=0.25 um (250 nm)(2.5 volt) hspice 49 level psice level7

MODEL CMOSP PMOS ( LEVEL = 7
+VERSION = 3.1 TNOM = 27 TOX = 5.7E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.6193382
+K1 = 0.5275326 K2 = 0.0281819 K3 = 0
+K3B = 11.249555 W0 = 1E-6 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 3.1920483 DVT1 = 0.4901788 DVT2 = -0.0295257
+U0 = 185.1288894 UA = 3.40616E-9 UB = 3.640498E-20
+UC = -6.35238E-11 VSAT = 1.975064E5 A0 = 0.4156696
+AGS = 0.0702036 B0 = 3.111154E-6 B1 = 5E-6
+KETA = 0.0253118 A1 = 2.421043E-4 A2 = 0.6754231
+RDSW = 866.896668 PRWG = 0.0362726 PRWB = -0.293946
+WR = 1 WINT = 6.519911E-9 LINT = 2.210804E-8
+XL = 3E-8 XW = 0 DWG = -2.423118E-8
+DWB = 3.052612E-8 VOFF = -0.1161062 NFACTOR = 1.2546896
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.7241245 ETAB = -0.3675267
+DSUB = 1.1734643 PCLM = 1.0837457 PDIBLC1 = 9.608442E-4
+PDIBLC2 = 0.0176785 PDIBLCB = -9.605935E-4 DROUT = 0.0735541
+PSCBE1 = 1.579442E10 PSCBE2 = 6.707105E-9 PVAG = 0.0409261
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL = 0
+WLN = 1 WW = 0 WWN = 1
+WWL = 0 LL = 0 LLN = 1
+LW = 0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 5.11E-10
+CGSO = 5.11E-10 CGBO = 1E-11 CJ = 1.882953E-3
+PB = 0.99 MJ = 0.4690946 CJSW = 3.018356E-10
+PBSW = 0.8137064 MJSW = 0.3299497 CF = 0
+PVTH0 = 5.268963E-3 PRDSW = -2.2622317 PK2 = 3.952008E-3
+WKETA = -7.69819E-3 LKETA = -0.0119828 )



.MODEL CMOSN NMOS ( LEVEL = 7
+VERSION = 3.1 TNOM = 27 TOX = 5.7E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.4273342
+K1 = 0.3922983 K2 = 0.0185825 K3 = 1E-3
+K3B = 2.0947677 W0 = 2.171779E-7 NLX = 1.919758E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 7.137212E-3 DVT1 = 6.066487E-3 DVT2 = -0.3025397
+U0 = 403.1776038 UA = -3.60743E-12 UB = 1.323051E-18
+UC = 2.575123E-11 VSAT = 1.616298E5 A0 = 1.4626549
+AGS = 0.3136349 B0 = 3.080869E-8 B1 = -1E-7
+KETA = 5.462411E-3 A1 = 4.653219E-4 A2 = 0.6191129
+RDSW = 345.624986 PRWG = 0.3183394 PRWB = -0.1441065
+WR = 1 WINT = 8.107812E-9 LINT = 3.375523E-9
+XL = 3E-8 XW = 0 DWG = 6.420502E-10
+DWB = 1.042094E-8 VOFF = -0.1083577 NFACTOR = 1.1884386
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 4.914545E-3 ETAB = 4.215338E-4
+DSUB = 0.0313287 PCLM = 1.2088426 PDIBLC1 = 0.7240447
+PDIBLC2 = 5.120303E-3 PDIBLCB = -0.0443076 DROUT = 0.7752992
+PSCBE1 = 4.451333E8 PSCBE2 = 5E-10 PVAG = 0.2068286
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL = 0
+WLN = 1 WW = -1.22182E-16 WWN = 1.2127
+WWL = 0 LL = 0 LLN = 1
+LW = 0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 6.33E-10
+CGSO = 6.33E-10 CGBO = 1E-11 CJ = 1.766171E-3
+PB = 0.9577677 MJ = 0.4579102 CJSW = 3.931544E-10
+PBSW = 0.99 MJSW = 0.2722644 CF = 0
+PVTH0 = -2.126483E-3 PRDSW = -24.2435379 PK2 = -4.788094E-4
+WKETA = 1.430792E-3 LKETA = -6.548592E-3 )

BSIM MODELS VERSION 4.2 FOR ORCAD 16.2

******** BSIM4.1.0 Model Card for NMOS ********

** The BSIM4 model card below was not extracted/obtained from/based on

** any real technologies. It should not be used for any other purposes

** except for benchmarking the implementation of BSIM4.1.0 against BSIM

** Team's standard results using SPICE3f5.

**** Weidong Liu, Xiaodong Jin, Mark Cao, and Chenming Hu 10/11/2000.

　

** Model: BSIM4.1.0

** Berkeley SPICE3f5 Compatible

** Lmin=0.12 Lmax=10 Wmin=0.6 Wmax=20

** By Weidong Liu 10/11/2000

.MODEL N1 NMOS LEVEL=8 VERSION=4.1.0 TNOM=27

+ EPSROX=3.9 TOXE=3e-9 TOXP=3e-9 TOXM=3e-9 TOXREF=3e-9 DTOX=0

+ MOBMOD=0 RDSMOD=0 IGCMOD=1 IGBMOD=1 DIOMOD=1 CAPMOD=2

+ RGATEMOD=1 RBODYMOD=1 TRNQSMOD=0 ACNQSMOD=0 FNOIMOD=1

+ TNOIMOD=0 PERMOD=1 GEOMOD=1 PARAMCHK=1 BINUNIT=1

+ NDEP=1.7e17 NGATE=9e19 VTH0=0.42 PHIN=0 XJ=9e-8 NSD=1e20

+ VFB=-0.76 K1=0.33 K2=-1.87e-2 K3=80 K3b=0 W0=2.5e-6 KT1=-0.11

+ KT1L=0 KT2=2.2e-2 LPE0=5.75e-8 LPEB=2.3e-10 DVT0=2.89 DVT1=0.53

+ DVT2=-3.2e-2 DVT0W=0 DVT1W=0 DVT2W=0 DVTP0=7.32e-7 DVTP1=0.12

+ DSUB=0.058 ETA0=0.001 ETAB=0

+ CDSC=2.58e-4 CDSCD=6.1e-8 CDSCB=0 CIT=0 NFACTOR=1.1 VOFF=-0.02 VOFFL=0

+ MINV=0.05 VSAT=9.2e4 AT=3.3e4 U0=4.19e-2 UA=8.7e-16 UB=3.06e-18

+ UC=4.6e-13 UTE=-1.5 UA1=4.31e-9 UB1=7.61e-18 UC1=-5.6e-11

+ RDSW=369.4 RDW=184.7 RSW=184.7 PRWG=3.22e-8 PRWB=6.8e-11 WR=1

+ RDSWMIN=0 RDWMIN=0 RSWMIN=0 PRT=0 A0=1.1 AGS=1e-20 B0=-1e-20

+ B1=0 KETA=-0.047 A1=0 A2=1 DELTA=0.014 PVAG=1e-20 PCLM=6.28e-4

+ PDITS=0.2 PDITSL=2.3e6 PDITSD=0.23 FPROUT=0.2 PDIBLCB=3.4e-8

+ PDIBLC1=0.81 DROUT=0.56 PDIBLC2=9.84e-06 PSCBE1=8.14e8 PSCBE2=9.58e-07

+ LINT=5e-9 WINT=5e-9 DWG=0 DWB=0 WL=0 WW=0 WWL=0

+ WLN=1 WWN=1 LL=0 LW=0 LWL=0 LLN=1 LWN=1

+ XGW=3e-7 XGL=4e-8 NGCON=1 RSHG=0.4 XRCRG1=12 XRCRG2=5

+ DMCG=5e-6 DMCI=5e-6 DMDG=5e-6 DMCGT=6e-7 DWJ=4.5e-8 RSH=6

+ RBDB=15 RBPD=15 RBSB=15 RBPS=15 RBPB=5 GBMIN=1e-10

+ CGSO=7.43e-10 CGDO=7.43e-10 CGBO=2.56e-11 CGSL=1e-14 CGDL=1e-14

+ CKAPPAS=0.5 CKAPPAD=0.5 NOFF=0.9 VOFFCV=0.02 ACDE=1 MOIN=15 XPART=0

+ JSS=1e-4 JSWS=1e-11 JSWGS=1e-10 CJS=5e-4 CJSWS=5e-10 CJSWGS=3e-10

+ PBS=1 PBSWS=1 PBSWGS=1 NJS=1 XTIS=3 MJS=0.5 MJSWS=0.33 MJSWGS=0.33

+ XJBVS=1 BVS=10 IJTHSFWD=1e-2 IJTHSREV=1e-3

+ JSD=1e-4 JSWD=1e-11 JSWGD=1e-10 CJD=5e-4 CJSWD=5e-10 CJSWGD=5e-10

+ PBD=1 PBSWD=1 PBSWGD=1 NJD=1 XTID=3 MJD=0.5 MJSWD=0.33 MJSWGD=0.33

+ XJBVD=1 BVD=10 IJTHDFWD=1e-2 IJTHDREV=1e-3

+ TCJ=1e-3 TCJSW=1e-3 TCJSWG=1e-3 TPB=0.005 TPBSW=0.005 TPBSWG=0.005

+ ALPHA0=7.4e-2 ALPHA1=0.005 BETA0=30 AGIDL=2e-4 BGIDL=2.1e9 CGIDL=2e-4

+ EGIDL=0.8 AIGC=0.043 BIGC=0.0054 CIGC=0.0075 AIGSD=0.043 BIGSD=0.0054

+ CIGSD=0.0075 DLCIG=2.2e-8 AIGBACC=0.043 BIGBACC=0.0054 CIGBACC=0.0075

+ AIGBINV=0.35 BIGBINV=0.03 CIGBINV=0.006 NIGC=1 NIGBACC=1 NIGBINV=3

+ NTOX=1 EIGBINV=1.1 PIGCD=1.0 POXEDGE=1

** EnD

******** BSIM4.1.0 Model Card for PMOS ********

** The BSIM4 model card below was not extracted/obtained from/based on

** any real technologies. It should not be used for any other purposes

** except for benchmarking the implementation of BSIM4.1.0 against BSIM

** Team's standard results using SPICE3f5.

**** Weidong Liu, Xiaodong Jin, Mark Cao, and Chenming Hu 10/11/2000.

　

** Model: BSIM4.1.0

** Berkeley SPICE3f5 Compatible

** Lmin=0.12 Lmax=10 Wmin=0.6 Wmax=20

** By Weidong Liu 10/11/2000

.MODEL P1 PMOS LEVEL=8 VERSION=4.1.0 TNOM=27

+ EPSROX=3.9 TOXE=3e-9 TOXP=3e-9 TOXM=3e-9 TOXREF=3e-9 DTOX=0

+ MOBMOD=0 RDSMOD=0 IGCMOD=1 IGBMOD=1 DIOMOD=1 CAPMOD=2

+ RGATEMOD=1 RBODYMOD=1 TRNQSMOD=0 ACNQSMOD=0 FNOIMOD=1

+ TNOIMOD=0 PERMOD=1 GEOMOD=1 PARAMCHK=1 BINUNIT=1

+ NDEP=1.7e17 NGATE=9e19 VTH0=-0.42 PHIN=0 XJ=9e-8 NSD=1e20

+ VFB=0.76 K1=0.33 K2=-1.87e-2 K3=80 K3b=0 W0=2.5e-6 KT1=-0.11

+ KT1L=0 KT2=2.2e-2 LPE0=5.75e-8 LPEB=2.3e-10 DVT0=2.89 DVT1=0.53

+ DVT2=-3.2e-2 DVT0W=0 DVT1W=0 DVT2W=0 DVTP0=7.32e-7 DVTP1=0.12

+ DSUB=0.058 ETA0=0.001 ETAB=0

+ CDSC=2.58e-4 CDSCD=6.1e-8 CDSCB=0 CIT=0 NFACTOR=1.1 VOFF=-0.02 VOFFL=0

+ MINV=0.05 VSAT=9.2e4 AT=3.3e4 U0=4.19e-2 UA=8.7e-16 UB=3.06e-18

+ UC=4.6e-13 UTE=-1.5 UA1=4.31e-9 UB1=7.61e-18 UC1=-5.6e-11

+ RDSW=369.4 RDW=184.7 RSW=184.7 PRWG=3.22e-8 PRWB=6.8e-11 WR=1

+ RDSWMIN=0 RDWMIN=0 RSWMIN=0 PRT=0 A0=1.1 AGS=1e-20 B0=-1e-20

+ B1=0 KETA=-0.047 A1=0 A2=1 DELTA=0.014 PVAG=1e-20 PCLM=6.28e-4

+ PDITS=0.2 PDITSL=2.3e6 PDITSD=0.23 FPROUT=0.2 PDIBLCB=3.4e-8

+ PDIBLC1=0.81 DROUT=0.56 PDIBLC2=9.84e-06 PSCBE1=8.14e8 PSCBE2=9.58e-07

+ LINT=5e-9 WINT=5e-9 DWG=0 DWB=0 WL=0 WW=0 WWL=0

+ WLN=1 WWN=1 LL=0 LW=0 LWL=0 LLN=1 LWN=1

+ XGW=3e-7 XGL=4e-8 NGCON=1 RSHG=0.4 XRCRG1=12 XRCRG2=5

+ DMCG=5e-6 DMCI=5e-6 DMDG=5e-6 DMCGT=6e-7 DWJ=4.5e-8 RSH=6

+ RBDB=15 RBPD=15 RBSB=15 RBPS=15 RBPB=5 GBMIN=1e-10

+ CGSO=7.43e-10 CGDO=7.43e-10 CGBO=2.56e-11 CGSL=1e-14 CGDL=1e-14

+ CKAPPAS=0.5 CKAPPAD=0.5 NOFF=0.9 VOFFCV=0.02 ACDE=1 MOIN=15 XPART=0

+ JSS=1e-4 JSWS=1e-11 JSWGS=1e-10 CJS=5e-4 CJSWS=5e-10 CJSWGS=3e-10

+ PBS=1 PBSWS=1 PBSWGS=1 NJS=1 XTIS=3 MJS=0.5 MJSWS=0.33 MJSWGS=0.33

+ XJBVS=1 BVS=10 IJTHSFWD=1e-2 IJTHSREV=1e-3

+ JSD=1e-4 JSWD=1e-11 JSWGD=1e-10 CJD=5e-4 CJSWD=5e-10 CJSWGD=5e-10

+ PBD=1 PBSWD=1 PBSWGD=1 NJD=1 XTID=3 MJD=0.5 MJSWD=0.33 MJSWGD=0.33

+ XJBVD=1 BVD=10 IJTHDFWD=1e-2 IJTHDREV=1e-3

+ TCJ=1e-3 TCJSW=1e-3 TCJSWG=1e-3 TPB=0.005 TPBSW=0.005 TPBSWG=0.005

+ ALPHA0=7.4e-2 ALPHA1=0.005 BETA0=30 AGIDL=2e-4 BGIDL=2.1e9 CGIDL=2e-4

+ EGIDL=0.8 AIGC=0.043 BIGC=0.0054 CIGC=0.0075 AIGSD=0.043 BIGSD=0.0054

+ CIGSD=0.0075 DLCIG=2.2e-8 AIGBACC=0.043 BIGBACC=0.0054 CIGBACC=0.0075

+ AIGBINV=0.35 BIGBINV=0.03 CIGBINV=0.006 NIGC=1 NIGBACC=1 NIGBINV=3

+ NTOX=1 EIGBINV=1.1 PIGCD=1.0 POXEDGE=1

** End

cadence tutorial video

http://lsmwww.epfl.ch/Education/CadenceTutorial/explanations/spec.html
https://ece.osu.edu/computing-resources/software-packages/cadence/tutorials
https://sites.google.com/a/eng.ucsd.edu/ece-165/ece-165---winter-2013/cadence-tutorial
http://www.ece.rice.edu/~cavallar/cadence/tutorial/
http://eda.engineering.wustl.edu/wiki/index.php/Tutorials:Cadence:AdvancedTopics
http://eda.engineering.wustl.edu/wiki/index.php/Tutorials:Cadence:AdvancedTopics
http://www.vtvt.ece.vt.edu/vlsidesign/tutorialSystemC_install.php
http://analog.ece.utk.edu/Cadence/Introduction.htm

FREE OPEN SOURCE CODE SITES

SOURCE CODES FOR MATLAB,VHDL,C,C++ ETC.

ASIC-WORLD
C-TO-VERILOG

FPGA RELATED
JOHN'S FPGA
OPENCORES
VERILOGCOURSETEAM


 

SPICE LINKS

http://www.uta.edu/ee/hw/pspice/
http://www.seas.upenn.edu/~jan/spice/spice.overview.html#Switches
http://ngspice.sourceforge.net/tutorials.html
http://ngspice.sourceforge.net/spices.html
http://ngspice.sourceforge.net/resources.html
http://www.cppsim.com/index.html
http://www.layouteditor.net/
http://www.geda-project.org/

Circuit Elements with memories

G7 memristor

LAY OUT DESIGN RULES FOR CMOS N-WELL PROCESS

Layout rule

Insulated Gate Bipolar Transistors (IGBTs)

STICK DIAGRAM CMOS TECHNOLOGY

MIT VLSI LINKS

http://home.etf.rs/~vm/tutorial/vlsi/vlsi/part1.html
http://www.vlsitechnology.org/html/layout_rules.html
http://www.vlsi-world.com/component/option,com_fireboard/Itemid,37/func,view/id,116/catid,5/
CAD tools (VLSI MIT)
ANALYSIS AND DESIGN OF DIGITAL INTEGRATED CIRCUIT
http://bwrc.eecs.berkeley.edu/IcBook/slides.htm
INTRODUCTION TO VLSI (VERILOG)
http://6004.csail.mit.edu/6.371/handouts.html
http://www.ece.virginia.edu/~mrs8n/cadence/tutorial5.html

VERY IMPORTANT NPTEL LINKS FOR VLSI

http://www.satishkashyap.com/p/video-lectures-from-iit-professors-not.html : very imp vlsi circiut
http://nptel.iitm.ac.in/video.php?subjectId=106102062  :  Introduction to Computer Architecture (very imp for flash controller design)
http://nptel.iitm.ac.in/courses/106105033/     : High Performance Computer Architecture (Video) Under Review (very imp for flash controller design)
http://nptel.iitm.ac.in/courses/106108055/   :   High Performance Computing (Video) >> Programs and Data (very imp for flash controller design)
http://www.youtube.com/playlist?list=PLE995EF1D8630E34F :youtube channel
http://www.satishkashyap.com/2012/03/iit-video-lectures-on-analog-vlsi.html (not avilable on nptel)
http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html
http://esd.cs.ucr.edu/labs/tutorial/
http://www.satishkashyap.com/2012/02/first-course-on-vlsi-design-and-cad.html
http://nptel.iitm.ac.in/courses/117106034/57    VLSI Data Conversion Circuits (Video) Under Review
http://nptel.iitm.ac.in/courses/108108031/     An Introduction to Electronics Systems Packaging (Video)

http://nptel.iitm.ac.in/courses/115102014/      >> Physics >> Electronics (Video)
http://nptel.iitm.ac.in/video.php?subjectId=108106069   :Digital Integrated Circuits (Video)
http://nptel.iitm.ac.in/courses/106105034/     Low Power VLSI Circuits & Systems (Video)
http://nptel.iitm.ac.in/courses/117108038/     Circuits for Analog System Design (Video) >> Transistor Amplifier
http://nptel.iitm.ac.in/courses/106103016/     VLSI Design Verification and Test (Web) Under Review
http://nptel.iitm.ac.in/video.php?subjectId=106105083    Electronic Design Automation (Video)(verilog)
http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_II/index.php
http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/index.php

http://nptel.iitm.ac.in/video.php?subjectId=117106093   >>VLSI Technology (Video) >> 1 - Introduction on VLSI Design

                                           
http://nptel.iitm.ac.in/courses/117108038/                  Circuits for Analog System Design (Video) >> Transistor Amplifier
http://nptel.iitm.ac.in/courses/117106034/                  VLSI Data Conversion Circuits (Video) Under Review >> Introduction to Data Conversion


http://nptel.iitm.ac.in/video.php?subjectId=117106092   : VLSI Circuits (Video) >> 1 - Introduction to VLSI Design


http://nptel.iitm.ac.in/video.php?subjectId=117106087    :>> Electronics for Analog Signal Processing - I (Video) >> 1 - Introduction

http://nptel.iitm.ac.in/courses/117102012/   :RF Integrated Circuits (Video) Under Review >> RF system basic architectures

http://nptel.iitm.ac.in/video.php?subjectId=117106091  : Solid State Devices (Video) >> 1 - Introduction on Solid State Devices




http://www.cdeep.iitb.ac.in/nptel/Electrical%20&%20Comm%20Engg/VLSI%20Design/Course%20Objective.htm

http://nptel.iitm.ac.in/video.php?subjectId=117105085  >Probability and Random Processes (Video)

http://nptel.iitm.ac.in/courses/111105041/ >>Probability and Statistics (Video) >> Algebra of Sets - I

http://nptel.iitm.ac.in/syllabus/111104025/     Mathematics >> Calculus of Variations and Integral Equations (Video)